This night we get another leap second, meaning that the last second of today is not 23:59:59 but 23:59:60 instead. The last time this happened was on June 30, 2012 and lead to issues on several servers due to bugs in the Linux kernel. Since then these bugs were fixed and also methods of hiding the leap second altogether were implemented. Here you can find a good overview over different configurations of kernel, ntpd and tzdata and how a leap second will be handled using these configurations. What is missing here is how a setup using systemd-timesyncd instead of ntpd will handle this situation.
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Zynq DDR self-refresh
The Xilinx Zynq SoC supports disabling the DDR3 memory controller and the corresponding clocks to save energy. The memory can be put into self-refresh mode to retain its data. Inspired by a thread on the Xilinx forums I measured the actual effect of this power saving method on a Digilent ZedBoard.
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XST and the difficulty of proper addition
More than a year ago I faced a strange issue with a hardware design on a Virtex-5 FPGA. Basically an addition of multiple values had no effect at all. Out of curiosity I reproduced this issue and now here are the details about what seems to be a serious bug in the XST synthesis tool for Virtex-5 FPGAs bundled with ISE 14.7.
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XPS on RHEL 7 / CentOS 7
Officially the ISE suite is not supported to run on RHEL / CentOS 7. But since time moves on and Vivado nowadays is supported on those systems you may be tempted to run the ISE tools on this system as well.
If you face the issue that XPS just shows a blank window and even XPS project files are opened as text files, the following will probably solve this issue:
yum install mesa-libGLU
By now this was also mentioned on a Xilinx forum thread but I thought I’d post it anyway.
Setting up Xilinx development tools on Debian
Debian is not a supported system for running the Xilinx developments tools. That does not mean you cannot use them on Debian. Here is a quick overview over the necessary steps to get them running on Jessie.
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Zynq ACP AxCACHE & AxUSER signals
If you want to use the AXI_ACP interface on a Xilinx Zynq SoC for coherent memory access from the PL, you have to set the AxUSER and AxCACHE signals accordingly. Unfortunately the Zynq TRM in section 3.5.1 only tells you how to set ARUSER[0], ARCACHE[1] and AWUSER[0], AWCACHE[1], respectively. So, what to do with the other bits?
Posts in the Xilinx forums suggest that most people just set all bits of AxUSER and AxCACHE to 1 and this typically works. For a description of all possible values have a look at ARM’s documentation for the Cortex-A9 and PL 310 IP cores that are used in the Zynq SoC:
Stock Debian Jessie on the Raspberry Pi 2
Yet another IT related blog
One of the neat things in IT is that answers to a lot of questions can be found on the internet. Public documentation, forums and blogs contain lots of valuable information and if you face a problem it’s likely that some other people struggled with it before and already found a solution.
This blog is the place where I will post about issues I faced and where simple solutions were not available yet on the internet or did not fit my needs. So, yet another IT related blog… But hopefully it will be of value for some people, just as a lot of other blogs have been of value for me.