System Administration, Reconfigurable Computing and Other Random Topics

Zynq ACP AxCACHE & AxUSER signals

If you want to use the AXI_ACP interface on a Xilinx Zynq SoC for coherent memory access from the PL, you have to set the AxUSER and AxCACHE signals accordingly. Unfortunately the Zynq TRM in section 3.5.1 only tells you how to set ARUSER[0]ARCACHE[1] and AWUSER[0]AWCACHE[1], respectively. So, what to do with the other bits?

Posts in the Xilinx forums suggest that most people just set all bits of AxUSER and AxCACHE to 1 and this typically works. For a description of all possible values have a look at ARM’s documentation for the Cortex-A9 and PL 310 IP cores that are used in the Zynq SoC:

Yet another IT related blog

One of the neat things in IT is that answers to a lot of questions can be found on the internet. Public documentation, forums and blogs contain lots of valuable information and if you face a problem it’s likely that some other people struggled with it before and already found a solution.

This blog is the place where I will post about issues I faced and where simple solutions were not available yet on the internet or did not fit my needs. So, yet another IT related blog… But hopefully it will be of value for some people, just as a lot of other blogs have been of value for me.