Recently I grabbed my trusted old Avnet / Digilent ZedBoard to test how well the current Xilinx tools work with this now a decade old platform. However, I was facing a weird issue: The serial output by the Zynq PL was only received via USB on my computer when I was sending characters via UART from my computer to the PL as well. As soon as there was a pause in communication, any further serial output by the PL was silently dropped.Read More
If you want to measure elapsed time in a bare-metal application on the Xilinx Zynq SoC—for example to measure how long your external accelerator takes to get a result—you will soon notice that typical methods do not work. But there is a simple and precise replacement for those methods.
The Xilinx Zynq SoC supports disabling the DDR3 memory controller and the corresponding clocks to save energy. The memory can be put into self-refresh mode to retain its data. Inspired by a thread on the Xilinx forums I measured the actual effect of this power saving method on a Digilent ZedBoard.
More than a year ago I faced a strange issue with a hardware design on a Virtex-5 FPGA. Basically an addition of multiple values had no effect at all. Out of curiosity I reproduced this issue and now here are the details about what seems to be a serious bug in the XST synthesis tool for Virtex-5 FPGAs bundled with ISE 14.7.
Officially the ISE suite is not supported to run on RHEL / CentOS 7. But since time moves on and Vivado nowadays is supported on those systems you may be tempted to run the ISE tools on this system as well.
If you face the issue that XPS just shows a blank window and even XPS project files are opened as text files, the following will probably solve this issue:
yum install mesa-libGLU
By now this was also mentioned on a Xilinx forum thread but I thought I’d post it anyway.
Debian is not a supported system for running the Xilinx developments tools. That does not mean you cannot use them on Debian. Here is a quick overview over the necessary steps to get them running on Jessie.
If you want to use the AXI_ACP interface on a Xilinx Zynq SoC for coherent memory access from the PL, you have to set the AxUSER and AxCACHE signals accordingly. Unfortunately the Zynq TRM in section 3.5.1 only tells you how to set ARUSER, ARCACHE and AWUSER, AWCACHE, respectively. So, what to do with the other bits?
Posts in the Xilinx forums suggest that most people just set all bits of AxUSER and AxCACHE to 1 and this typically works. For a description of all possible values have a look at ARM’s documentation for the Cortex-A9 and PL 310 IP cores that are used in the Zynq SoC: