Recently I grabbed my trusted old Avnet / Digilent ZedBoard to test how well the current Xilinx tools work with this now a decade old platform. However, I was facing a weird issue: The serial output by the Zynq PL was only received via USB on my computer when I was sending characters via UART from my computer to the PL as well. As soon as there was a pause in communication, any further serial output by the PL was silently dropped.Read More
Zynq DDR self-refresh
The Xilinx Zynq SoC supports disabling the DDR3 memory controller and the corresponding clocks to save energy. The memory can be put into self-refresh mode to retain its data. Inspired by a thread on the Xilinx forums I measured the actual effect of this power saving method on a Digilent ZedBoard.